(1) Field of the Invention
The present invention relates to processes used to fabricate semiconductor devices, and more specifically to a method used to create conductive vias and conductive interconnect structures, using a damascene patterning process.
(2) Description of the Prior Art
The use of sub-micron features, or micro-miniaturization, has allowed the semiconductor industry to increase device density for very large scale integrated, (VLSI), semiconductor chips. The evolution to micro-miniaturization has been highlighted by advances in specific semiconductor fabrication disciplines such as photolithography, and dry etching. The development of mode sophisticated exposure cameras, as well as the use of more photo-sensitive materials, have allowed sub-micron images, in photoresist layers, to be routinely obtained. In addition the advent of advanced dry etching tools, and processes, have in turn allowed the sub-micron images, in masking photoresist layers, to be successfully transferred to underlying materials, used in the fabrication of VLSI chips. However to continue to decrease the size of semiconductor chips, specific process or structural innovations, are also needed, in addition to the advances in specific semiconductor fabrication disciplines. One such process innovation has been the use of dual damascene patterning, for attainment of metal lines and metal vias. The dual damascene procedure features the creation of a pattern, opened in an insulator layer, with the dual damascene pattern comprised of an underlying narrow diameter opening, and a wider diameter, overlying opening. Filling of the dual damascene opening, in the insulator layer, with metal, results a metal structure comprised of a metal interconnect structure, located in the wider diameter opening, overlying a metal via, located in the narrower diameter opening, in the dual damascene opening. The dual damascene procedure, in which both metal interconnects, and metal vias, are formed using a single metal fill, and only one metal patterning, or removal procedure, offers advantages over conventional procedures, in which a metal fill, and a metal patterning procedure, would have to be used for both the metal via structure, and the metal interconnect structure.
A critical step, used for creation of a dual damascene opening, is the ability to form, or to terminate, the wider diameter opening, in a top portion of an insulator layer, without transferring this wider diameter opening, to the bottom portion of the insulator layer, where the narrow diameter opening is to be formed. One method used to address this concern is the use of a stop layer, placed between both portions of the insulator layer. After forming the desired narrow diameter openings, in the stop layer, which resides on the unetched lower portion of insulator layer, the top portion of insulator layer is deposited. A photoresist shape, featuring the wider diameter opening, is used as a mask to create the wider diameter opening, in the top portion of the insulator layer, exposing the stop layer, which is comprised of narrow diameter openings. A selective dry etch procedure, is then use to form the narrow diameter openings, in the bottom portion of the insulator layer, exposed in the narrow diameter openings, in the stop layer. However to successfully prevent unwanted etching of the bottom portion of insulator layer, a thick stop layer, exhibiting a low removal rate in the dry etching process used for insulator etching, is employed. Therefore if silicon oxide, with a dielectric constant of only about 3.9 is used, as the insulator layer, minimizing performance degrading capacitances, the stop layer used is usually comprised of silicon nitride, allowing the desired dry etching selectivity to be realized. However since a continuous, except for the narrow diameter openings, silicon nitride, stop layer, with a dielectric constant of about 7, is needed, performance concerns exist.
This invention will describe a dual damascene patterning procedure, used to create metal vias and interconnects, in openings formed in a composite insulator layer, and featuring the use of a silicon nitride stop layer, strategically placed between silicon oxide layers, of the composite insulator layer. However this invention will describe a novel patterning sequence, featuring the use of small area, silicon nitride islands, used for the needed stop layer, thus resulting in a less capacitance increase, than counterparts fabricated using larger area, silicon nitride stop layers. Prior art, such as Avanzino et al, in U.S. Pat. No. 5,686,354, as well as Huang et al, in U.S. Pat. No. 5,635,423, describe dual damascene processes, however these prior art do not show the stop layer, comprised of small area, silicon nitride islands, used in the present invention, offering less capacitance than counterparts described in the prior art.